1. Field of the Invention
The invention relates to a semiconductor device and a method for manufacturing the same, particularly to a semiconductor device having a metal insulator semiconductor field effect transistor (MIS FET) characterized by high current drive power and having a channel formed of strained Si, strained SiGe or Ge.
2. Description of the Related Art
In recent years, it is considered for the purpose of realizing high-performance and high-function of a CMOS circuit device to use channel materials of high mobility such as strained Si or strained SiGe (including Ge).
The strained Si has an tensile strain in in-plain direction of the substrate. The band structure of the strained Si varies due to this tensile strain, so that both electron and hole mobilities increase in comparison with an unstrained Si. Usually, the strained Si is formed on a lattice relaxed SiGe of a greater lattice constant by epitaxial growth.
The strain in the strained Si layer increases as the Ge composition of a SiGe template increases, resulting in increasing the mobility. If CMOS is fabricated by MOSFET having the strained Si channel, it is expected to operate at a higher speed than Si-CMOS of the same size.
On the other hand, the strained SiGe has a compressive strain in in-plain direction of the substrate and varies in its band structure due to this compressive strain, resulting in that the hole mobility increases in comparison with an unstrained Si. However, increase of the electron mobility is smaller in comparison with the hole mobility when the Ge fraction is not sufficiently high. When the SiGe channels have compressive strain of around 1% and Ge composition larger than around 80%, both electron mobility and hole mobility increase more than 2 times in comparison with the unstrained Si. As a result, the maximum enhancement of the mobility is provided in a pure Ge channel. If CMOS is fabricated by MOSFET having a strained SiGe of high Ge composition, it is expected to operate at higher speed than the strained Si-CMOS as well as Si-CMOS of the same size.
Further, the strained SGOI (SiGe-on-Insulator)-MOSFET (for example, MOSFET described in a non-patent literature (T. Tezuka et al., IEDM Technical Digests, p. 946 (2001)) fabricated by combination of the strained SiGe-MOSFET with a SOI (Si-on-Insulator) structure has merits obtained by the SOI structure such as decrease of junction capacitance, decrease of device size with the impurity density being lowered, as well as merit obtained by the high carrier mobility of the strained SiGe channel. Accordingly, if a CMOS logic circuit is fabricated by a MOSFET of a strained SGOI channel, an operation of higher-speed and lower power is expected.
However, since the SiGe has a band gap smaller than a conventional Si, a junction leakage current increases inevitably, resulting in lowering a breakdown voltage. Accordingly, for the SOC (System-on-Chip) application that integrates in a single LSI chip a plurality of kinds of MOSFETs such as LOP (Low Operation Power)-MOSFET for a low power operation and low standby power operation, LSP (Low Stand-by Power)-MOSFET and high breakdown voltage MOSFET as well as HP (High performance)-MOSFET for high speed operation, it is preferable that a SGOI channel is used for the HP-MOSFET and a bulk Si or SOI or a strained SOI is used for the LOP- and LSP-MOSFET.
An example which integrates strained SOI-MOSFETs and SGOI-MOSFETs is provided by, for example, a patent literature 1 (Japanese Patent Laid-Open No. 2001-160594). In this literature, the n channel has a bi-layer structure of a lattice-relaxed SiGe and a strained Si. Accordingly, SiGe layers are used in both p, n channels. However, because SiGe has a band gap smaller than a conventional Si regardless of strain or non-strain, a junction leakage current increases necessarily, resulting in lowering a withstand voltage. Accordingly, for SOC (System-on-Chip) application, it is difficult due to SiGe layer to satisfy specifications of leakage and breakdown voltage in devices other than HP-MOSFET.
In this way the conventional art provides a configuration that integrates a SOI-MOSFET and a SGOI-MOSFET for the purposed of realizing high-performance and high-function of CMOS circuit device. However, since this configuration uses a SiGe layer for both p, n channels, it is difficult due to the SiGe layer to satisfy specifications of leakage and breakdown voltage in devices other than HP-MOSFET. In other words, it is difficult to realize both high-speed operation and low-power operation.
Further, in reducing the size of a MOSFET of SOI structure, it is necessary to decrease a thickness of a channel layer on a buried oxide film. In particular, it is necessary for realizing an operation of a fully depleted device to decrease a film thickness to about ¼ of a gate length. This request means that it is necessary for making a gate length, for example, 20 nm to make a channel film thickness (additional value of film thickness of a strained Si and that of a lattice-relaxed SiGe in nMOSFET of the patent literature 1) nm. It is very difficult to realize such decreasing of film thickness in a multi-layer structure while maintaining productivity.
The present invention is to provide a semiconductor device capable of realizing an integrated circuit device having both high-speed operation and low-power operation by combining bulk Si, a SOI thin film, a SGOI thin film, etc. and a method of manufacturing the same.